A Test Procedure for Boundary Scan Circuitry in PLDs and FPGAs

A test procedure for testing mainly the boundary scan cells, and testing partially the test access port controller in programmable logic devices, and field programmable gate array devices, is suggested. The test procedure involves; the configuration of programmable logic devices or field programmable gate array device, the application of test vectors, and finally the verification of the response. These steps are repeated with two different configurations of the device under test, to ensure high faults coverage. Both the configuration, and the application of test vectors, is performed through the joint test access group port of the device under test. The parts of the boundary scan circuit and the type of faults which are covered are